// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  dum_reg_reg_offset_field.h
// Project line  :  
// Department    :  K5
// Author        :  AnthonySixta
// Version       :  1.0
// Date          :  2013/5/31
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  AnthonySixta 2018/03/16 17:46:49 Create file
// ******************************************************************************

#ifndef __DUM_REG_REG_OFFSET_FIELD_H__
#define __DUM_REG_REG_OFFSET_FIELD_H__

#define DUM_REG_DDRC_IOTEST_CTRL0_LEN    32
#define DUM_REG_DDRC_IOTEST_CTRL0_OFFSET 0

#define DUM_REG_DDRC_IOTEST_CTRL1_LEN    16
#define DUM_REG_DDRC_IOTEST_CTRL1_OFFSET 0

#define DUM_REG_DDRC_IETEST_CTRL0_LEN    32
#define DUM_REG_DDRC_IETEST_CTRL0_OFFSET 0

#define DUM_REG_DDRC_IETEST_CTRL1_LEN    16
#define DUM_REG_DDRC_IETEST_CTRL1_OFFSET 0

#define DUM_REG_DDRC_O_CTRL0_LEN    32
#define DUM_REG_DDRC_O_CTRL0_OFFSET 0

#define DUM_REG_DDRC_O_CTRL1_LEN    16
#define DUM_REG_DDRC_O_CTRL1_OFFSET 0

#define DUM_REG_DDRC_OE_CTRL0_LEN    32
#define DUM_REG_DDRC_OE_CTRL0_OFFSET 0

#define DUM_REG_DDRC_OE_CTRL1_LEN    16
#define DUM_REG_DDRC_OE_CTRL1_OFFSET 0

#define DUM_REG_DDRC_IE_CTRL0_LEN    32
#define DUM_REG_DDRC_IE_CTRL0_OFFSET 0

#define DUM_REG_DDRC_IE_CTRL1_LEN    16
#define DUM_REG_DDRC_IE_CTRL1_OFFSET 0

#define DUM_REG_DDRC_NE_CTRL0_LEN    32
#define DUM_REG_DDRC_NE_CTRL0_OFFSET 0

#define DUM_REG_DDRC_NE_CTRL1_LEN    16
#define DUM_REG_DDRC_NE_CTRL1_OFFSET 0

#define DUM_REG_DDRC_ODTTEST_CTRL0_LEN    32
#define DUM_REG_DDRC_ODTTEST_CTRL0_OFFSET 0

#define DUM_REG_DDRC_ODTTEST_CTRL1_LEN    16
#define DUM_REG_DDRC_ODTTEST_CTRL1_OFFSET 0

#define DUM_REG_DDRC_ODTEN_CTRL0_LEN    32
#define DUM_REG_DDRC_ODTEN_CTRL0_OFFSET 0

#define DUM_REG_DDRC_ODTEN_CTRL1_LEN    16
#define DUM_REG_DDRC_ODTEN_CTRL1_OFFSET 0

#define DUM_REG_DDRC_IOTST_I_STAT0_LEN    32
#define DUM_REG_DDRC_IOTST_I_STAT0_OFFSET 0

#define DUM_REG_DDRC_IOTST_I_STAT1_LEN    16
#define DUM_REG_DDRC_IOTST_I_STAT1_OFFSET 0

#define DUM_REG_M3_MERR_INTSTS_LEN      1
#define DUM_REG_M3_MERR_INTSTS_OFFSET   11
#define DUM_REG_M3_SERR_INTSTS_LEN      1
#define DUM_REG_M3_SERR_INTSTS_OFFSET   10
#define DUM_REG_M3_MERR_RINT_LEN        1
#define DUM_REG_M3_MERR_RINT_OFFSET     9
#define DUM_REG_M3_SERR_RINT_LEN        1
#define DUM_REG_M3_SERR_RINT_OFFSET     8
#define DUM_REG_M3_MERR_INT_MASK_LEN    1
#define DUM_REG_M3_MERR_INT_MASK_OFFSET 5
#define DUM_REG_M3_SERR_INT_MASK_LEN    1
#define DUM_REG_M3_SERR_INT_MASK_OFFSET 4
#define DUM_REG_M3_MEM_ECC_BYP_LEN      1
#define DUM_REG_M3_MEM_ECC_BYP_OFFSET   1
#define DUM_REG_M3_MEM_WB_LEN           1
#define DUM_REG_M3_MEM_WB_OFFSET        0

#define DUM_REG_DMC_BW_PRI_LEN     3
#define DUM_REG_DMC_BW_PRI_OFFSET  4
#define DUM_REG_DMC_BW_WIN_LEN     2
#define DUM_REG_DMC_BW_WIN_OFFSET  2
#define DUM_REG_DMC_BW_TYPE_LEN    1
#define DUM_REG_DMC_BW_TYPE_OFFSET 1
#define DUM_REG_DMC_BW_EN_LEN      1
#define DUM_REG_DMC_BW_EN_OFFSET   0

#define DUM_REG_DMC_BW_LVL1_LEN    16
#define DUM_REG_DMC_BW_LVL1_OFFSET 16
#define DUM_REG_DMC_BW_LVL0_LEN    16
#define DUM_REG_DMC_BW_LVL0_OFFSET 0

#define DUM_REG_DMC_BW_CMD_ID_LEN    18
#define DUM_REG_DMC_BW_CMD_ID_OFFSET 0

#define DUM_REG_DMC_BW_CMD_IDMASK_LEN    18
#define DUM_REG_DMC_BW_CMD_IDMASK_OFFSET 0

#define DUM_REG_EN_LEN    1
#define DUM_REG_EN_OFFSET 0

#define DUM_REG_ADDR_LEN    32
#define DUM_REG_ADDR_OFFSET 0

#define DUM_REG_ERR_INJECT_MASK1_LEN    8
#define DUM_REG_ERR_INJECT_MASK1_OFFSET 24
#define DUM_REG_ERR_INJECT_MASK0_LEN    8
#define DUM_REG_ERR_INJECT_MASK0_OFFSET 16
#define DUM_REG_ERR_INJECT_BYTE1_LEN    5
#define DUM_REG_ERR_INJECT_BYTE1_OFFSET 9
#define DUM_REG_ERR_INJECT_BYTE0_LEN    5
#define DUM_REG_ERR_INJECT_BYTE0_OFFSET 4
#define DUM_REG_ERR_INJECT_MODE_LEN     2
#define DUM_REG_ERR_INJECT_MODE_OFFSET  0

#define DUM_REG_UERR_LEN    1
#define DUM_REG_UERR_OFFSET 1
#define DUM_REG_CERR_LEN    1
#define DUM_REG_CERR_OFFSET 0

#define DUM_REG_ADDR_LEN    32
#define DUM_REG_ADDR_OFFSET 0

#define DUM_REG_ADDR_LEN    32
#define DUM_REG_ADDR_OFFSET 0

#define DUM_REG_DATA_LEN    32
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    32
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    32
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    32
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    16
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    32
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    32
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    32
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    32
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_DATA_LEN    16
#define DUM_REG_DATA_OFFSET 0

#define DUM_REG_INBAND_UERR_INTMSK_LEN    1
#define DUM_REG_INBAND_UERR_INTMSK_OFFSET 1
#define DUM_REG_INBAND_CERR_INTMSK_LEN    1
#define DUM_REG_INBAND_CERR_INTMSK_OFFSET 0

#define DUM_REG_INBAND_UERR_RINT_LEN    1
#define DUM_REG_INBAND_UERR_RINT_OFFSET 1
#define DUM_REG_INBAND_CERR_RINT_LEN    1
#define DUM_REG_INBAND_CERR_RINT_OFFSET 0

#define DUM_REG_CERR_ID_LEN    32
#define DUM_REG_CERR_ID_OFFSET 0

#define DUM_REG_UERR_ID_LEN    32
#define DUM_REG_UERR_ID_OFFSET 0

#define DUM_REG_CERR_EXPECT_DATA0_LEN    32
#define DUM_REG_CERR_EXPECT_DATA0_OFFSET 0

#define DUM_REG_CERR_EXPECT_DATA1_LEN    32
#define DUM_REG_CERR_EXPECT_DATA1_OFFSET 0

#define DUM_REG_CERR_EXPECT_DATA2_LEN    32
#define DUM_REG_CERR_EXPECT_DATA2_OFFSET 0

#define DUM_REG_CERR_EXPECT_DATA3_LEN    32
#define DUM_REG_CERR_EXPECT_DATA3_OFFSET 0

#define DUM_REG_CERR_EXPECT_ECC_LEN    16
#define DUM_REG_CERR_EXPECT_ECC_OFFSET 0

#define DUM_REG_INBAND_ECC_CERR_CNT_LEN    32
#define DUM_REG_INBAND_ECC_CERR_CNT_OFFSET 0

#define DUM_REG_INBAND_ECC_UERR_CNT_LEN    32
#define DUM_REG_INBAND_ECC_UERR_CNT_OFFSET 0

#define DUM_REG_DMC_HIDDRPHY_REG_SLVERR_LEN    1
#define DUM_REG_DMC_HIDDRPHY_REG_SLVERR_OFFSET 0

#define DUM_REG_DBG_MODE_SEL_LEN    5
#define DUM_REG_DBG_MODE_SEL_OFFSET 0

#define DUM_REG_UCE_TEST_POINT_LEN    8
#define DUM_REG_UCE_TEST_POINT_OFFSET 16
#define DUM_REG_DBG_MODE_OUT_LEN      16
#define DUM_REG_DBG_MODE_OUT_OFFSET   0



#define DUM_REG_UCE_SYS_IDLE_LEN    1
#define DUM_REG_UCE_SYS_IDLE_OFFSET 1
#define DUM_REG_UCE_M3_IDLE_LEN     1
#define DUM_REG_UCE_M3_IDLE_OFFSET  0

#define DUM_REG_TZ_UCE_SECURE_N_LEN    1
#define DUM_REG_TZ_UCE_SECURE_N_OFFSET 1
#define DUM_REG_TZ_DMC_SECURE_N_LEN    1
#define DUM_REG_TZ_DMC_SECURE_N_OFFSET 0

#define DUM_REG_CLK_WR_EN_LEN    16
#define DUM_REG_CLK_WR_EN_OFFSET 16
#define DUM_REG_BYPASS_LEN       4
#define DUM_REG_BYPASS_OFFSET    12

#define DUM_REG_CLK_WR_EN_LEN           16
#define DUM_REG_CLK_WR_EN_OFFSET        16
#define DUM_REG_UC_H2H_M_GT_EN_LEN      1
#define DUM_REG_UC_H2H_M_GT_EN_OFFSET   14
#define DUM_REG_DMC_APB_GT_EN_LEN       1
#define DUM_REG_DMC_APB_GT_EN_OFFSET    6
#define DUM_REG_PHYUPD_REQEN_BYP_LEN    1
#define DUM_REG_PHYUPD_REQEN_BYP_OFFSET 0

#define DUM_REG_CLK_WR_EN_LEN            16
#define DUM_REG_CLK_WR_EN_OFFSET         16
#define DUM_REG_RS_NEG_TX_CLOCK_LEN      1
#define DUM_REG_RS_NEG_TX_CLOCK_OFFSET   8
#define DUM_REG_RS1_TX_CLOCK_LEN         1
#define DUM_REG_RS1_TX_CLOCK_OFFSET      7
#define DUM_REG_RS0_TX_CLOCK_LEN         1
#define DUM_REG_RS0_TX_CLOCK_OFFSET      6
#define DUM_REG_RS2_RX_CLOCK_LEN         1
#define DUM_REG_RS2_RX_CLOCK_OFFSET      5
#define DUM_REG_RS1_RX_CLOCK_LEN         1
#define DUM_REG_RS1_RX_CLOCK_OFFSET      4
#define DUM_REG_RS_NEG_RX_CLOCK_LEN      1
#define DUM_REG_RS_NEG_RX_CLOCK_OFFSET   3
#define DUM_REG_DFI_CLK_DLYLINE_LEN      1
#define DUM_REG_DFI_CLK_DLYLINE_OFFSET   2
#define DUM_REG_DFI_CLK_DDRPHY_LEN       1
#define DUM_REG_DFI_CLK_DDRPHY_OFFSET    1
#define DUM_REG_CLK_DDRPHY_APB_AC_LEN    1
#define DUM_REG_CLK_DDRPHY_APB_AC_OFFSET 0

#define DUM_REG_CLK_WR_EN_LEN                   16
#define DUM_REG_CLK_WR_EN_OFFSET                16
#define DUM_REG_SC_UCE_BUS_AUTOGT_BYPASS_LEN    1
#define DUM_REG_SC_UCE_BUS_AUTOGT_BYPASS_OFFSET 14
#define DUM_REG_DDRPHY_REF_CLK_SEL_LEN          1
#define DUM_REG_DDRPHY_REF_CLK_SEL_OFFSET       13
#define DUM_REG_ICG_EN_UCE_32K_LEN              1
#define DUM_REG_ICG_EN_UCE_32K_OFFSET           12
#define DUM_REG_ICG_EN_PERSTAT_LEN              1
#define DUM_REG_ICG_EN_PERSTAT_OFFSET           11
#define DUM_REG_ICG_EN_UCE_ENGINE_LEN           1
#define DUM_REG_ICG_EN_UCE_ENGINE_OFFSET        10
#define DUM_REG_ICG_EN_DMC_FREE_LEN             1
#define DUM_REG_ICG_EN_DMC_FREE_OFFSET          9
#define DUM_REG_ICG_EN_DDRPHY_BYPASS_LEN        1
#define DUM_REG_ICG_EN_DDRPHY_BYPASS_OFFSET     8
#define DUM_REG_ICG_EN_DDRPHY_REF_LEN           1
#define DUM_REG_ICG_EN_DDRPHY_REF_OFFSET        7
#define DUM_REG_ICG_EN_DFI_DMC_LEN              1
#define DUM_REG_ICG_EN_DFI_DMC_OFFSET           6
#define DUM_REG_ICG_EN_DFI_PHY_LEN              1
#define DUM_REG_ICG_EN_DFI_PHY_OFFSET           5
#define DUM_REG_ICG_EN_DFI_PACK_LEN             1
#define DUM_REG_ICG_EN_DFI_PACK_OFFSET          4
#define DUM_REG_ICG_EN_UCE_BUS_LEN              1
#define DUM_REG_ICG_EN_UCE_BUS_OFFSET           3
#define DUM_REG_ICG_EN_UCE_LEN                  1
#define DUM_REG_ICG_EN_UCE_OFFSET               2
#define DUM_REG_ICG_EN_PACK_APB_LEN             1
#define DUM_REG_ICG_EN_PACK_APB_OFFSET          1
#define DUM_REG_ICG_EN_DMC_APB_LEN              1
#define DUM_REG_ICG_EN_DMC_APB_OFFSET           0

#define DUM_REG_CLK_WR_EN_LEN              16
#define DUM_REG_CLK_WR_EN_OFFSET           16
#define DUM_REG_UC_DIV_LEN                 2
#define DUM_REG_UC_DIV_OFFSET              8
#define DUM_REG_SRST_REQ_UCE_32K_LEN       1
#define DUM_REG_SRST_REQ_UCE_32K_OFFSET    7
#define DUM_REG_SRST_REQ_DFI_LEN           1
#define DUM_REG_SRST_REQ_DFI_OFFSET        6
#define DUM_REG_SRST_REQ_UCE_ENGINE_LEN    1
#define DUM_REG_SRST_REQ_UCE_ENGINE_OFFSET 5
#define DUM_REG_SRST_REQ_DMC_FREE_LEN      1
#define DUM_REG_SRST_REQ_DMC_FREE_OFFSET   4
#define DUM_REG_SRST_REQ_DMC_LEN           1
#define DUM_REG_SRST_REQ_DMC_OFFSET        3
#define DUM_REG_SRST_REQ_PACK_LEN          1
#define DUM_REG_SRST_REQ_PACK_OFFSET       2
#define DUM_REG_SRST_REQ_UCEM3_LEN         1
#define DUM_REG_SRST_REQ_UCEM3_OFFSET      1
#define DUM_REG_SRST_REQ_UCE_LEN           1
#define DUM_REG_SRST_REQ_UCE_OFFSET        0

#endif // __DUM_REG_REG_OFFSET_FIELD_H__
